M42h HDMI2.2信号发生器/协议分析仪

Key Features
• Verify the 16b/18b encoding for Fixed Rate Link (FRL) Packets in both 3 and 4 lane configurations
• Use generator or analyzer in three (3) Lane configuration mode at 3Gbps/6Gbps data rates and four (4) Lane configurations at 6Gbps through 24Gbps (96Gbps aggregate)
• Video generator function supports TMDS and FRL for resolutions up to 8K, 10K and 12K with DSC compression and Optimized Video Timing (OVT) format
• View captured FRL and TMDS data elements graphically in Event Plot and in Data Decode table; use searching and filtering to find data
• View FRL packet mapping into Character Blocks and Character Block mapping into Super Blocks
• Verify Display Stream Compression (DSC) on FRL, DSC capable source or sink devices.
• Run FRL and DSC source/sink compliance tests
• Run eARC the full suite of compliance tests on an eARC Tx or Rx device
• Run TMDS source/sink compliance tests
• Run HDCP 2.3 source, sink & repeater compliance tests
• View TMDS video, protocol, data island, preamble and control elements
• Monitor of FRL Link Training transactions in the Auxiliary Channel Analyzer utility to show SCDC reads and writes over the DDC channel
• Passively monitor DDC channel in TMDS or FRL mode (FRL mode requires custom cable)
• View Lane Error Counts and Reed Solomon Corrections Count in the SCDC CED registers
• Verify the eARC common mode channel on either an eARC Tx or Rx device
• Run Gaming-VRR, FVA and QMS-VRR tests
• Run test automation for compliance tests with API